Debugging?ext_808404September 27 2011, 20:46:43 UTC
Hi, thanks for the excellent teardown. Did you get any further with this hack?
I've taken apart one of these and trying to figure out which debug interface it uses, JTAG or SWD. Not all test pins are marked, and the two relevant that are marked just say: "TP_TDO/SWD" and "TP_TRST3"
Use of JTAG "TRST" might mean they use the JTAG configuration, which would be nice since OpenOCD has support for bus pirate JTAG on the STM32 MCU.
Though the marking "TP_TDO/SWD" is confusing since the ST data sheet states that pins are JTCK/SWCLK or JTMS/SWDIO for SWD.
I've not really done much with it beyond the python stuff.. running my own code on it does appeal, but I've not thought of a good thing to do with it yet.
Re: Debugging?ext_808404October 3 2011, 19:03:05 UTC
We'll if you are interested I've got as far as getting OpenOCD JTAG using a bus pirate to work.
I've done flash dump, and a quick disassemble, but going further means some serious reverse-engineering of assembler. I've not done much probing on the PCB, but it's a multi-layer board so it doesn't expose much of the CPU I/O anyway.
Having a PCB schematic at this point would be a blast :-)
Re: Debugging?ext_808404January 9 2012, 01:02:58 UTC
I know you posted this a couple of months back but is there any chance i could have a copy of the jtag rom dump? You truely have balls of steel soldering onto those pads!
Comments 18
I've taken apart one of these and trying to figure out which debug interface it uses, JTAG or SWD. Not all test pins are marked, and the two relevant that are marked just say: "TP_TDO/SWD" and "TP_TRST3"
Use of JTAG "TRST" might mean they use the JTAG configuration, which would be nice since OpenOCD has support for bus pirate JTAG on the STM32 MCU.
Though the marking "TP_TDO/SWD" is confusing since the ST data sheet states that pins are JTCK/SWCLK or JTMS/SWDIO for SWD.
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I've done flash dump, and a quick disassemble, but going further means some serious reverse-engineering of assembler. I've not done much probing on the PCB, but it's a multi-layer board so it doesn't expose much of the CPU I/O anyway.
Having a PCB schematic at this point would be a blast :-)
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My email is: aj563 @nospam york.ac.uk
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Thanks.
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