(no subject)

Apr 28, 2008 10:39

Heh, so I started examining core dumps from OpenOCD, which immediately uncovered this totally farcical bit of code:


int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
{
stm32x_flash_bank_t *stm32x_info = NULL;
target_t *target = bank->target;
u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
int i, reg, bit;
int status;
u32 protection;

stm32x_info = bank->driver_priv;

if (target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}

if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
{
LOG_WARNING("sector start/end incorrect - stm32 has 4K sector protection");
return ERROR_FLASH_SECTOR_INVALID;
}

/* each bit refers to a 4bank protection */
target_read_u32(target, STM32_FLASH_WRPR, &protection);

prot_reg[0] = (u16)protection;
prot_reg[1] = (u16)(protection >> 8);
prot_reg[2] = (u16)(protection >> 16);
prot_reg[3] = (u16)(protection >> 24);

for (i = first; i <= last; i++)
{
reg = (i / 4) / 8;
bit = (i / 4) - (reg * 8);

if( set )
prot_reg[reg] &= ~(1 << bit);
else
prot_reg[reg] |= (1 << bit);
}

if ((status = stm32x_erase_options(bank)) != ERROR_OK)
return status;

stm32x_info->option_bytes.protection[0] = prot_reg[0];
stm32x_info->option_bytes.protection[1] = prot_reg[1];
stm32x_info->option_bytes.protection[2] = prot_reg[2];
stm32x_info->option_bytes.protection[3] = prot_reg[3];

return stm32x_write_options(bank);
}

This made me distrust the information reported by OpenOCD's flash info 0 command, so I tried to write the flash memory using flash write_bank 0 "main.bin" 0 despite not "removing" the "protection" reported by the former command, and it worked. I had assumed that this protection mechanism referred to the Memory Protection Unit (MPU) provided by the STM32, however, this is apparently not the case.

Now I have a flashing LED. OpenOCD is incredibly rough around the edges, but I finally figured out the issues preventing me from loading programs onto my development board, and soon I will be writing my own programs for the ARM Cortex-M3.
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