Prolonging block-level verification delays the start of chip-level verification, but inadequate block-level verification prolongs chip-level verification. There are two solutions to this dilemma: use constrained random verification techniques, or use ABV* with RTL checking and formal property verification.
the only book i have handy is a slide package from a Verification Seminar last week :p
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the only book i have handy is a slide package from a Verification Seminar last week :p
*Assertion Based Verification
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